Thursday, March 5, 2009
World’s Fastest Microprocessors
2003: Intel® Pentium® M Processor
2002: Intel® Itanium™ 2 Processor
2001: Intel® Itanium™ Processor
2001: Intel® Xeon™ Processor
2000: Intel® Pentium® 4 Processor
1999: Intel® Pentium® III Xeon™ Processor
1999: Intel® Pentium® III Processor
1999: Intel® Celeron® Processor
1998: Intel® Pentium II Xeon Processor
1997: Intel® Pentium® II Processor
1995: Intel® Pentium® Pro Processor
1989: Intel486™ DX CPU Microprocessor
1985: Intel386™ Microprocessor
1982: 286 Microprocessor
1978: 8086-8088 Microprocessor
1974: 8080 Microprocessor
1972: 8008 Microprocessor
1971: 4004 Microprocessor
486DX2 Microprocessor
Cyrix Integrated Circuits - 486DX2 Microprocessor
Wednesday, March 4, 2009
Versa 8051 Microcontroller
The VRS51L2070 is the newest product in Ramtron's Versa 8051 MCU family. This fully integrated, high performance system-on-chip incorporates an advanced 40-MIPS, single-cycle 8051-core, 64KB Flash with in-system/in-application programming, 4 KB SRAM, a JTAG program/debug interface, digital signal processing (DSP) extensions and a robust digital peripheral set. Operating at 3.3 volts over the entire industrial temperature range, the VRS51L2070 is ideal for embedded data acquisition, sensor and control applications in the industrial, medical, consumer, instrumentation and automotive markets.
40 MHz, single-cycle 8051 processor: This is one of the fastest 8-bit processors on the market. Its advanced core can deliver up to 40 MIPS throughput and is instruction-compatible with standard 8051s for smooth device migration.
MULT/ACCU/DIV Unit with 32-bit barrel shifter: This hardware calculation engine significantly outperforms 8-bit processors when executing DSP operations (FIR filtering, sensor output linearization, multiple-byte arithmetic operations, etc). It performs 16-bit signed multiplication and 32-bit addition in one cycle (at 40 MHz) and 16-bit signed division in 5 cycles (at 40 MHz). The barrel shifter enables logic/arithmetic shift operations.
40-MHz precision internal oscillator: The VRS51L2070's internal oscillator provides 2-percent accuracy and cuts system costs by eliminating the need for an external oscillator.
JTAG Interface: For user-friendly and quick device programming and real-time, in-circuit debugging/emulation of the user application without the need for a costly emulator.
Dual UARTs with baud rate generator: The universal asynchronous receiver/transmitters operate at up to 1.25 Mb/s. Each UART incorporates a dedicated baud rate generator with 16-bit resolution and 4-bit micro baud rate adjustment.
Enhanced SPI: The communication speed on the serial peripheral interface can be configured up to 20 Mb/s, and transactions are adjustable from 1 to 32 bits.
PWCs: Two pulse-width counter modules provide advanced timer control, simplifying event duration measurement.
PWMs: The VRS51L2070 incorporates eight pulse-width modulators with up to 16-bit adjustable resolution. Each PWM includes its own timer, which can also be used as general-purpose timers. Other support peripherals include an I²C interface, three 16-bit general purpose timers/counters with three timer capture inputs, a watchdog timer, and 49 interrupts that share 16 interrupt vectors. The VRS51L2070 is available in a QFP-64 package. The VRS51L2070 is currently sampling and costs under $4 in volume.
8051 Micro controller
8081 Micro conroller :
The Intel 8051 is a Harvard architecture, single chip microcontroller (µC) which was developed by Intel in 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s, but has today largely been superseded by a vast range of faster and/or functionally enhanced 8051-compatible devices manufactured by more than 20 independent manufacturers including Atmel, Infineon Technologies (formerly Siemens AG), Maxim Integrated Products (via its Dallas Semiconductor subsidiary), NXP (formerly Philips Semiconductor), Nuvoton (formerly Winbond), ST Microelectronics, Silicon Laboratories (formerly Cygnal), Texas Instruments and Cypress Semiconductor. Intel's official designation for the 8051 family of µCs is MCS 51.
Intel's original 8051 family was developed using NMOS technology, but later versions, identified by a letter "C" in their name, e.g. 80C51, used CMOS technology and were less power-hungry than their NMOS predecessors - this made them eminently more suitable for battery-powered devices.
Important features and applications:
- It provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a single package
- 8-bit ALU, Accumulator and Registers; hence it is an 8-bit microcontroller
- 8-bit data bus - It can access 8 bits of data in one operation
- 16-bit address bus - It can access 216 memory locations - 64 kB ( 65536 locations ) each of RAM and ROM
- On-chip RAM - 128 bytes ("Data Memory")
- On-chip ROM - 4 kB ("Program Memory")
- Four byte bi-directional input/output port
- UART (serial port)
- Two 16-bit Counter/timers
- Two-level interrupt priority
- Power saving mode
A particularly useful feature of the 8051 core is the inclusion of a boolean processing engine which allows bit-level boolean logic operations to be carried out directly and efficiently on internal registers and RAM. This feature helped to cement the 8051's popularity in industrial control applications. Another valued feature is that it has four separate register sets, which can be used to greatly reduce interrupt latency compared to the more common method of storing interrupt context on a stack.
The 8051 UARTs make it simple to use the chip as a serial communications interface. External pins can be configured to connect to internal shift registers in a variety of ways, and the internal timers can also be used, allowing serial communications in a number of modes, both synchronous and asynchronous. Some modes allow communications with no external components. A mode compatible with an RS-485 multi-point communications environment is achievable, but the 8051's real strength is fitting in with existing ad-hoc protocols, e.g when controlling serial-controlled devices.
Once a UART - and a timer, if necessary, have been configured, the programmer needs only to write a simple interrupt routine to refill the 'send' shift register whenever the last bit is shifted out by the UART and/or empty the full 'receive' shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.
8051 based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM (16 bytes of which are bit-addressable), up to 128 bytes of I/O, 512 bytes to 64 kB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in the external data space. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle, and have clock frequencies of up to 100 MHz, and are thus capable of an even greater number of instructions per second. All SILabs, some Dallas and a few Atmel devices have single cycle cores
Even higher speed single cycle 8051 cores, in the range 130 MHz to 150 MHz, are now available in internet downloadable form for use in programmable logic devices such as FPGAs, and at many hundreds of MHz in ASICs.
Common features included in modern 8051 based microcontrollers include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable Flash ROM program memory, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host interfaces, PWM generators, analog comparators, A/D and D/A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, and extra power saving modes.
Programming:
Several C compilers are available for the 8051, most of which feature extensions that allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to 8051 specific hardware features such as the multiple register banks and bit manipulation instructions. Other high level languages such as Forth, BASIC, Pascal/Object Pascal, PL/M and Modula 2 are available for the 8051, but they are less widely used than C and assembly.
Related processors
The 8051's predecessor, the 8048, was used in the keyboard of the first IBM PC, where it converted keypresses into the serial data stream which is sent to the main unit of the computer. The 8048 and derivatives are still used today[update] for basic model keyboards.
The 8031 was a cut down version of the original Intel 8051 that did not contain any internal program memory (ROM). To use this chip external ROM had to be added containing the program that the 8031 would fetch and execute.
The 8052 was an enhanced version of the original 8051 that featured 256 bytes of internal RAM instead of 128 bytes, 8 kB of ROM instead of 4 kB, and a third 16-bit timer. The 8032 had these same features except for the internal ROM program memory. The 8052 and 8032 are largely considered to be obsolete because these features and more are included in nearly all modern 8051 based microcontrollers.
Intel 8742 8-bit microcontroller
Microcontroller
A microcontroller (also MCU or µC) is a small computer on a single integrated circuit consisting of a relatively simple CPU combined with support functions such as a crystal oscillator, timers, watchdog, serial and analog I/O etc. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a, typically small, read/write memory.
Thus, in contrast to the microprocessors used in personal computers and other high perfomance applications, simplicity is emphasized. Some microcontrollers may operate at clock frequencies as low as 32KHz, as this is adequate for many typical applications, enabling low power consumption (milliwatts or microwatts). They will generally have the ability to retain functionality while waiting for an event such as a button press or other interrupt; power consumption while sleeping (CPU clock and most peripherals off) may be just nanowatts, making many of them well suited for long lasting battery applications.
Microcontrollers are used in automatically controlled products and devices, such as automobile engine control systems, remote controls, office machines, appliances, power tools, and toys. By reducing the size and cost compared to a design that uses a separate microprocessor, memory, and input/output devices, microcontrollers make it economical to digitally control even more devices and processes
Embedded design:
The majority of computer systems in use today are embedded in other machinery, such as automobiles, telephones, appliances, and peripherals for computer systems. These are called embedded systems. While some embedded systems are very sophisticated, many have minimal requirements for memory and program length, with no operating system, and low software complexity. Typical input and output devices include switches, relays, solenoids, LEDs, small or custom LCD displays, radio frequency devices, and sensors for data such as temperature, humidity, light level etc. Embedded systems usually have no keyboard, screen, disks, printers, or other recognizable I/O devices of a personal computer, and may lack human interaction devices of any kind.
Interrupts:
It is mandatory that microcontrollers provide real time response to events in the embedded system they are controlling. When certain events occur, an interrupt system can signal the processor to suspend processing the current instruction sequence and to begin an interrupt service routine (ISR). The ISR will perform any processing required based on the source of the interrupt before returning to the original instruction sequence. Possible interrupt sources are device dependent, and often include events such as an internal timer overflow, completing an analog to digital conversion, a logic level change on an input such as from a button being pressed, and data received on a communication link. Where power consumption is important as in battery operated devices, interrupts may also wake a microcontroller from a low power sleep state where the processor is halted until required to do something by a peripheral event.
Programs:
Microcontroller programs must fit in the available on-chip program memory, since it would be costly to provide a system with external, expandable, memory. Compilers and assembly language are used to turn high-level language programs into a compact machine code for storage in the microcontroller's memory. Depending on the device, the program memory may be permanent, read-only memory that can only be programmed at the factory, or program memory may be field-alterable flash or erasable read-only memory.
Other microcontroller features:
Since embedded processors are usually used to control devices, they sometimes need to accept input from the device they are controlling. This is the purpose of the analog to digital converter. Since processors are built to interpret and process digital data, i.e. 1s and 0s, they won't be able to do anything with the analog signals that may be being sent to it by a device. So the analog to digital converter is used to convert the incoming data into a form that the processor can recognize. There is also a digital to analog converter that allows the processor to send data to the device it is controlling.
In addition to the converters, many embedded microprocessors include a variety of timers as well. One of the most common types of timers is the Programmable Interval Timer, or PIT for short. A PIT just counts down from some value to zero. Once it reaches zero, it sends an interrupt to the processor indicating that it has finished counting. This is useful for devices such as thermostats, which periodically test the temperature around them to see if they need to turn the air conditioner on, the heater on, etc.
Time Processing Unit or TPU for short. Is essentially just another timer, but more sophisticated. In addition to counting down, the TPU can detect input events, generate output events, and other useful operations.
Dedicated Pulse Width Modulation (PWM) block makes it possible for the CPU to control power converters, resistive loads, motors, etc., without using lots of CPU resources in tight timer loops.
Universal Asynchronous Receiver/Transmitter (UART) block makes it possible to receive and transmit data over a serial line with very little load on the CPU.
For those wanting ethernet one can use an external chip like Crystal Semiconductor CS8900A, Realtek RTL8019, or Microchip ENC 28J60. All of them allow easy interfacing with low pin count.
Higher integration:
In contrast to general-purpose CPUs, microcontrollers may not implement an external address or data bus as they integrate RAM and non-volatile memory on the same chip as the CPU. Using fewer pins, the chip can be placed in a much smaller, cheaper package.
Integrating the memory and other peripherals on a single chip and testing them as a unit increases the cost of that chip, but often results in decreased net cost of the embedded system as a whole. Even if the cost of a CPU that has integrated peripherals is slightly more than the cost of a CPU + external peripherals, having fewer chips typically allows a smaller and cheaper circuit board, and reduces the labor required to assemble and test the circuit board.
A microcontroller is a single integrated circuit, commonly with the following features:
- central processing unit - ranging from small and simple 4-bit processors to complex 32- or 64-bit processors
- discrete input and output bits, allowing control or detection of the logic state of an individual package pin
- serial input/output such as serial ports (UARTs)
- other serial communications interfaces like I²C, Serial Peripheral Interface and Controller
- Area Network for system interconnect
- peripherals such as timers, event counters, PWM generators, and watchdog
- volatile memory (RAM) for data storage
- ROM, EPROM, EEPROM or Flash memory for program and operating parameter storage
- clock generator - often an oscillator for a quartz timing crystal, resonator or RC circuit
- many include analog-to-digital converters
- in-circuit programming and debugging support
This integration drastically reduces the number of chips and the amount of wiring and circuit board space that would be needed to produce equivalent systems using separate chips. Furthermore, and on low pin count devices in particular, each pin may interface to several internal peripherals, with the pin function selected by software. This allows a part to be used in a wider variety of applications than if pins had dedicated functions. Microcontrollers have proved to be highly popular in embedded systems since their introduction in the 1970s.
Some microcontrollers use a Harvard architecture: separate memory buses for instructions and data, allowing accesses to take place concurrently. Where a Harvard architecture is used, instruction words for the processor may be a different bit size than the length of internal memory and registers; for example: 12-bit instructions used with 8-bit data registers.
The decision of which peripheral to integrate is often difficult. The microcontroller vendors often trade operating frequencies and system design flexibility against time-to-market requirements from their customers and overall lower system cost. Manufacturers have to balance the need to minimize the chip size against additional functionality.
Microcontroller architectures vary widely. Some designs include general-purpose microprocessor cores, with one or more ROM, RAM, or I/O functions integrated onto the package. Other designs are purpose built for control applications. A microcontroller instruction set usually has many instructions intended for bit-wise operations to make control programs more compact. For example, a general purpose processor might require several instructions to test a bit in a register and branch if the bit is set, where a microcontroller could have a single instruction to provide that commonly-required function.
Microcontrollers typically do not have a math coprocessor, so fixed point or floating point arithmetic are performed by program code.
Volumes:
About 55% of all CPUs sold in the world are 8-bit microcontrollers and microprocessors. According to Semico, Over 4 billion 8-bit microcontrollers were sold in 2006.
A typical home in a developed country is likely to have only four general-purpose microprocessors but around three dozen microcontrollers. A typical mid range automobile has as many as 30 or more microcontrollers. They can also be found in any electrical device: washing machines, microwave ovens, telephones etc.
Manufacturers have often produced special versions of their microcontrollers in order to help the hardware and software development of the target system. Originally these included EPROM versions that have a "window" on the top of the device through which program memory can be erased by ultra violet light, ready for reprogramming after a programming ("burn") and test cycle. Since 1998, EPROM versions are rare and have been replaced by EEPROM and flash, which are easier to use (can be erased electronically) and cheaper to manufacture.
Other versions may be available where the ROM is accessed as an external device rather than as internal memory, however these are becoming increasingly rare due to the widespread availability of cheap microcontroller programmers.
The use of field-programmable devices on a microcontroller may allow field update of the firmware or permit late factory revisions to products that have been assembled but not yet shipped. Programmable memory also reduces the lead time required for deployment of a new product.
Where hundreds of thousands of identical devices are required, using parts programmed at the time of manufacture can be an economical option. These 'Mask Programmed' parts have the program laid down in the same way as the logic of the chip, at the same time.
Programming environments:
Microcontrollers were originally programmed only in assembly language, but various high-level programming languages are now also in common use to target microcontrollers. These languages are either designed specially for the purpose, or versions of general purpose languages such as the C programming language. Compilers for general purpose languages will typically have some restrictions as well as enhancements to better support the unique characteristics of microcontrollers. Some microcontrollers have environments to aid developing certain types of applications. Microcontroller vendors often make tools freely available to make it easier to adopt their hardware.
Many microcontrollers are so quirky that they effectively require their own non-standard dialects of C, such as SDCC for the 8051, which prevent using standard tools (such as code libraries or static analysis tools) even for code unrelated to hardware features. Interpreters are often used to hide such low level quirks.
Interpreter firmware is also available for some microcontrollers. For example, BASIC on the early microcontrollers Intel 8052; BASIC and FORTH on the Zilog Z8 as well as some modern devices. Typically these interpreters support interactive programming.
Simulators are available for some microcontrollers, such as in Microchip's MPLAB environment. These allow a developer to analyse what the behaviour of the microcontroller and their program should be if they were using the actual part. A simulator will show the internal processor state and also that of the outputs, as well as allowing input signals to be generated. While on the one hand most simulators will be limited from being unable to simulate much other hardware in a system, they can exercise conditions that may otherwise be hard to reproduce at will in the physical implementation, and can be the quickest way to debug and analyse problems.
Recent microcontrollers are often integrated with on-chip debug circuitry that when accessed by an In-circuit emulator via JTAG, allow debugging of the firmware with a debugger.
Types of microcontrollers:
As of 2008 there are several common architectures:
MSP430 (16-bit)
CF (32-bit)
ARM
MIPS (32-bit PIC32)
S08
AVR
PIC (8-bit PIC16, PIC18, 16-bit dsPIC33 / PIC24)
V850
PowerPC ISE
PSoC (Programmable System-on-Chip)
Others typically are used in very narrow range of applications or are more like processors than microcontrollers
Interrupt latency:
In contrast to general-purpose computers, microcontrollers used in embedded systems often seek to minimize interrupt latency over instruction throughput.
When an electronic device causes an interrupt, the intermediate results, the registers, have to be saved before the software responsible for handling the interrupt can run, and then must be put back after it is finished. If there are more registers, this saving and restoring process takes more time, increasing the latency.
Low-latency MCUs generally have relatively few registers in their central processing units, or they have "shadow registers", a duplicate register set that is only used by the interrupt software.
List of Intel microprocessors 3
32-bit processors: NetBurst micro architecture
- 0.18 µm process technology (1.40 and 1.50 GHz)
Introduced November 20, 2000
L2 cache was 256 KB Advanced Transfer Cache (Integrated)
Processor Package Style was PGA423, PGA478
System Bus clock rate 400 MHz
SSE2 SIMD Extensions
Number of Transistors 42 million
Used in desktops and entry-level workstations - 0.18 µm process technology (1.7 GHz)
Introduced April 23, 2001 - 0.18 µm process technology (1.6 and 1.8 GHz)
Introduced July 2, 2001
Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in battery
Optimized Mode
Power <1>
- 0.18 µm process technology Willamette (1.9 and 2.0 GH0z)
Introduced August 27, 2001
Family 15 model 1 - Pentium 4 (2 GHz, 2.20 GHz)
Introduced January 7, 2002 - Pentium 4 (2.4 GHz)
Introduced April 2, 2002 - 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
Improved branch prediction and other microcodes tweaks
512 KB integrated L2 cache
Number of transistors 55 million
400 MHz system bus. - Family 15 model 2
- 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
533 MHz system bus. (3.06 includes Intel's hyper threading technology).
0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
800 MHz system bus (all versions include Hyper Threading)
6500 to 10000 MIPS
Itanium (chronological entry)
- Introduced 2001
- Official designation now Xeon, i.e. not "Pentium 4 Xeon"
- Xeon 1.4, 1.5, 1.7 GHz
Introduced May 21, 2001
L2 cache was 256 KB Advanced Transfer Cache (Integrated)
Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
System Bus clock rate 400 MHz
SSE2 SIMD Extensions
Used in high-performance and mid-range dual processor enabled workstations - Xeon 2.0 GHz and up to 3.6 GHz
Introduced September 25, 2001
Itanium 2 (chronological entry)
- Introduced July 2002
Mobile Pentium 4-M
- 0.13 µm process technology
- 55 million transistors
- cache L2 512 KB
- BUS a 400 MHz
- Supports up to 1 GB of DDR 266 MHz Memory
- Supports ACPI 2.0 and APM 1.2 System Power Management
- 1.3 V - 1.2 V (SpeedStep)
- Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
- Sleep Power 5 W (1.2 V)
- Deeper Sleep Power = 2.9 W (1.0 V)
1.40 GHz - 23 April 2002
1.50 GHz - 23 April 2002
1.60 GHz - 4 March 2002
1.70 GHz - 4 March 2002
1.80 GHz - 23 April 2002
1.90 GHz - 24 June 2002
2.00 GHz - 24 June 2002
2.20 GHz - 16 September 2002
2.40 GHz - 14 January 2003
2.40 GHz - 14 January 2003
2.50 GHz - 16 April 2003
2.60 GHz - 11 June 2003
- Introduced September 2003
- EE = "Extreme Edition"
- Built from the Xeon's "Gallatin" core, but with 2 MB cache
Pentium 4E
- Introduced February 2004
- built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
- 533 MHz system bus (2.4A and 2.8A only)
- Number of Transistors 125 million on 1 MB Models
- Number of Transistors 169 million on 2 MB Models
- 800 MHz system bus (all other models)
- Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
- The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.
- 7500 to 11000 MIPS
- LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
- The 6xx series has 2 MB L2 cache and Intel 64
Pentium 4F
- Introduced Spring 2004
- same core as 4E, "Prescott"
- 3.2–3.6 GHz
- starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated
64-bit processors: IA-64
- New instruction set, not at all related to x86.
- Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly
- Code name Merced
- Family 0x07
- Released May 29, 2001
- 733 MHz and 800 MHz
- 2MB cache
- All recalled and replaced by Itanium-II
- Family 0x1F
- Released July 2002
- 900 MHz - 1.6 GHz
- McKinley 900MHz 1.5MB cache, Model 0x0
- McKinley 1GHz, 3MB cache, Model 0x0
- Deerfield 1GHz, 1.5MB cache, Model 0x1
- Madison 1.3GHz, 3MB cache, Model 0x1
- Madison 1.4GHz, 4MB cache, Model 0x1
- Madison 1.5GHz, 6MB cache, Model 0x1
- Madison 1.67GHz, 9MB cache, Model 0x1
- Hondo 1.4GHz, 4MB cache, dual core MCM, Model 0x1
Pentium M (chronological entry)
- Introduced March 2003
Pentium 4EE, 4E (chronological entries)
- Introduced September 2003, February 2004, respectively
64-bit processors: Intel 64 - NetBurst
- Intel Extended Memory 64 Technology
- Mostly compatible with AMD's AMD64 architecture
- Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
Pentium 4F
- Prescott-2M built on 0.09 µm (90 nm) process technology
- 2.8-3.8 GHz (model numbers 6x0)
- Introduced February 20, 2005
- Same features as Prescott with the addition of:-
2 MB cache
Intel 64bit
Enhanced Intel SpeedStep Technology (EIST) - Cedar Mill built on 0.065 µm (65 nm) process technology
- 3.0-3.6 (model numbers 6x1)
- Introduced January 16, 2006
- die shrink of Prescott-2M
- Same features as Prescott-2M
Main article: List of Intel Pentium D microprocessors
- Dual-core microprocessor
- No Hyper-Threading
- 800(4x200) MHz front side bus
- Smithfield - 90 nm process technology (2.66–3.2 GHz)
Introduced May 26, 2005
2.66–3.2 GHz (model numbers 805-840)
Number of Transistors 230 million
1 MB x 2 (non-shared, 2 MB total) L2 cache
Cache coherency between cores requires communication over the FSB
Performance increase of 60% over similarly clocked Prescott
2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
Contains 2x Prescott dies in one package
- Presler - 65 nm process technology (2.8–3.6 GHz)
Introduced January 16, 2006
2.8–3.6 GHz (model numbers 915-960)
Number of Transistors 376 million
2 MB x 2 (non-shared, 4 MB total) L2 cache
Contains 2x Cedar Mill dies in one package
- Dual-core microprocessor
- Enabled Hyper-Threading
- 800(4x200) MHz front side bus
- Smithfield - 90 nm process technology (3.2 GHz)
Variants
Pentium 840 EE - 3.20 GHz (2 x 1 MB L2) - Presler - 65 nm process technology (3.46, 3.73)
2 MB x 2 (non-shared, 4 MB total) L2 cache
Variants
Pentium 955 EE - 3.46 GHz
Pentium 965 EE - 3.73 GHz
- Nocona
Introduced 2004 - Irwindale
Introduced 2004 - Cranford
Introduced April 2005
MP version of Nocona - Potomac
Introduced April 2005
Cranford with 8 MB of L3 cache - Paxville DP (2.8 GHz)
Introduced October 10, 2005
Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)
2.8 GHz
800 MT/s front side bus - Paxville MP - 90 nm process (2.67 - 3.0 GHz)
Introduced November 1, 2005
Dual-Core Xeon 7000 series
MP-capable version of Paxville DP
2 MB of L2 Cache (1 MB per core) or 4 MB of L2 (2 MB per core)
667 MT/s FSB or 800 MT/s FSB - Dempsey - 65 nm process (2.67 - 3.73 GHz)
Introduced May 23, 2006
Dual-Core Xeon 5000 series
MP version of Presler
667 MT/s or 1066 MT/s FSB
4 MB of L2 Cache (2 MB per core)
Socket J, also known as LGA 771. - Tulsa - 65 nm process (2.5 - 3.4 GHz)
Introduced August 29, 2006
Dual-Core Xeon 7100-series
Improved version of Paxville MP
667 MT/s or 800 MT/s FSB
64-bit processors: Intel 64 - Core microarchitecture
- Woodcrest - 65 nm process technology
Server and Workstation CPU (SMP support for dual CPU system)
Introduced June 26, 2006
Dual-Core
Intel VT, multiple OS support
EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
Execute Disable Bit
TXT, enhanced security hardware extensions
SSSE3 SIMD instructions
iAMT2 (Intel Active Management Technology), remotely manage computers - Variants
Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
Xeon 5148LV - 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) -- Low Voltage Edition - Clovertown - 65 nm process technology
Server and Workstation CPU (SMP support for dual CPU system)
Introduced Dec 13th 2006
Quad Core
Intel VT, multiple OS support
EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335
Execute Disable Bit
TXT, enhanced security hardware extensions
SSSE3 SIMD instructions
iAMT2 (Intel Active Management Technology), remotely manage computers - Variants
Xeon X5355 - 2.66 GHz (2x4 MB L2, 1333 MHz FSB, 105 W)
Xeon E5345 - 2.33 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
Xeon E5335 - 2.00 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
Xeon E5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
Xeon E5310 - 1.60 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
Xeon L5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 50 W)-- Low Voltage Edition
- Conroe - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two cores on one die
Introduced July 27, 2006
SSSE3 SIMD instructions
Number of Transistors 291 Million
Intel VT, multiple OS support
TXT, enhanced security hardware extensions
Execute Disable Bit
EIST (Enhanced Intel SpeedStep Technology)
iAMT2 (Intel Active Management Technology), remotely manage computers
LGA775
Variants
Core 2 Duo E6850 - 3.00 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6550 - 2.33 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB)
Core 2 Duo E6320 - 1.86 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB) - Conroe XE - 65 nm process technology
Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
Introduced July 27, 2006
same features as Conroe
LGA775
Variants
Core 2 Extreme X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB) - Allendale - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two CPUs on one die
Introduced January 21, 2007
SSSE3 SIMD instructions
Number of Transistors 167 Million
TXT, enhanced security hardware extensions
Execute Disable Bit
EIST (Enhanced Intel SpeedStep Technology)
iAMT2 (Intel Active Management Technology), remotely manage computers
LGA775
Variants
Core 2 Duo E4600 - 2.40 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4500 - 2.20 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4400 - 2.00 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4300 - 1.80 GHz (2 MB L2, 800 MHz FSB) - Merom - 65 nm process technology
Mobile CPU (SMP support restricted to 2 CPUs)
Introduced July 27, 2006
Family 6, Model 15, Stepping 10
same features as Conroe
Socket M / Socket P
Variants
Core 2 Duo T7800 - 2.60 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)
Core 2 Duo T7700 - 2.40 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7500 - 2.20 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7300 - 2.00 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7250 - 2.00 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7100 - 1.80 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB)
Core 2 Duo T5550 - 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5470 - 1.60 GHz (2 MB L2, 800 MHz FSB, no VT)
Core 2 Duo T5450 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5300 - 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)
Core 2 Duo T5270 - 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)
Core 2 Duo T5250 - 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)
Core 2 Duo L7500 - 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
Core 2 Duo L7400 - 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
Core 2 Duo L7300 - 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
Core 2 Duo L7200 - 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
Core 2 Duo U7700 - 1.33 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Core 2 Duo U7600 - 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Core 2 Duo U7500 - 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage) - Kentsfield - 65 nm process technology
Two dual-core cpu dies in one package.
Desktop CPU Quad Core (SMP support restricted to 4 CPUs)
Introduced December 13, 2006
same features as Conroe but with 4 CPU Cores
Number of Transistors 586 Million
Socket 775
Family 6, Model 15, Stepping 11
Variants
Core 2 Extreme QX6850 - 3 GHz (2x4 MB L2 Cache, 1333 MHz FSB)
Core 2 Extreme QX6800 - 2.93 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Apr 9th 07)
Core 2 Extreme QX6700 - 2.66 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Nov 14th 06)
Core 2 Quad Q6700 - 2.66 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Jul 22nd 07)
Core 2 Quad Q6600 - 2.40 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Jan 7th 07) - Wolfdale - 45 nm process technology
Die shrink of Conroe
Same features as Conroe with the addition of:-
50% more cache, 6 MB as opposed to 4 MB
Intel Trusted Execution Technology
SSE4 SIMD instructions
Number of Transistors 410 Million
Variants
Core 2 Duo E8600 - 3.33 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8500 - 3.16 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8400 - 3.00 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8300 - 2.83 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8200 - 2.66 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8190 - 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT) - Yorkfield - 45 nm process technology
Quad core CPU
Die shrink of Kentsfield
Contains 2x Wolfdale dual core dies in one package
Same features as Wolfdale
Number of Transistors 820 Million
Variants
Core 2 Extreme QX9770 - 3.2 GHz (2x6 MB L2, 1600 MHz FSB)
Core 2 Extreme QX9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
Core 2 Quad Q9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
Core 2 Quad Q9550 - 2.83 GHz (2x6 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9550s - 2.83 GHz (2x6 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9450 - 2.66 GHz (2x6 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9400 - 2.66 GHz (2x3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9400s - 2.66 GHz (2x3 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9300 - 2.5 GHz (2x3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8300 - 2.5 GHz (2x2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8200 - 2.33 GHz (2x2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8200s - 2.33 GHz (2x2 MB L2, 1333 MHz FSB, 65W TDP)
- Allendale - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two CPUs on one die
Introduced January 21, 2007
SSSE3 SIMD instructions
Number of Transistors 167 Million
TXT, enhanced security hardware extensions
Execute Disable Bit
EIST (Enhanced Intel SpeedStep Technology)
Variants
Intel Pentium E2220 - 2.40 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2200 - 2.20 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2180 - 2.00 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2160 - 1.80 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2140 - 1.60 GHz (1 MB L2, 800 MHz FSB) - Wolfdale 45 nm process technology
Intel Pentium E5400 - 2.70 GHz (2MB L2,800 MHz FSB)
Intel Pentium E5300 - 2.60 GHz (2MB L2,800 MHz FSB)
Intel Pentium E5200 - 2.50 GHz (2MB L2,800 MHz FSB)
- Merom-1024 65 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit, 64-bit
No SpeedStep technology, is not part of the 'Centrino' package
Variants
520 - 1.60 GHz
530 - 1.73 GHz
540 - 1.86 GHz
550 - 2.00 GHz
- Bloomfield - 45 nm process technology
256 KB L2 cache
8 MB L3 cache
front side bus replaced with QuickPath up to 6.4GT/s
Hyper-Threading is again included. This had previously been removed at the introduction of Core line
781 million transistors
introduced November 17, 2008
Variants
920 - 2.66 GHz
940 - 2.93 GHz
965 (extreme edition) - 3.20 GHz