Intel 4004: first single-chip microprocessor
- Introduced November 15, 1971
- Clock rate 740 kHz[1]
- 0.07 MIPS
- Bus Width 4 bits (multiplexed address/data due to limited pins)
- PMOS
- Number of Transistors 2,300 at 10 µm
- Addressable Memory 640 bytes
- Program Memory 4 KB (4 KB)
- One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
- Originally designed to be used in Busicom calculator
MCS-4 Family:
- 4004-CPU
- 4001-ROM & 4 Bit Port
- 4002-RAM & 4 Bit Port
- 4003-10 Bit Shift Register
- 4008-Memory+I/O Interface
- 4009-Memory+I/O Interface
MCS-40 Family:
- 4040-CPU
- 4101-1024-bit (256 x 4) Static RAM with separate I/O
- 4201-4MHz Clock Generator
- 4207-General Purpose Byte I/O Port
- 4209-General Purpose Byte I/O Port
- 4211-General Purpose Byte I/O Port
- 4265-Programmable General Purpose I/O Device
- 4269-Programmable Keyboard Display Device
- 4289-Standard Memory Interface for MCS-4/40
- 4308-8192-bit (1024 x 8) ROM w/ 4-bit I/O Ports
- 4316-16384-bit (2048 x 8) Static ROM
- 4702-2048-bit (256 x 8) EPROM
- 4801-5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
The 8-bit processors :
- Introduced April 1, 1972
- Clock rate 500 kHz (8008-1: 800 kHz)
- 0.05 MIPS
- Bus Width 8 bits (multiplexed address/data due to limited pins)
- Enhancement load PMOS logic
- Number of Transistors 3,500 at 10 µm
- Addressable memory 16 KB
- Typical in dumb terminals, general calculators, bottling machines
- Developed in tandem with 4004
- Originally intended for use in the Datapoint 2200 terminal
- Introduced April 1, 1974
- Clock rate 2 MHz
- 0.64 MIPS
- Bus Width 8 bits data, 16 bits address
- Enhancement load NMOS logic
- Number of Transistors 6,000
- Assembly language downwards compatible with 8008.
- Addressable memory 64 KB
- Up to 10X the performance of the 8008
- Used in the Altair 8800, Traffic light controller, cruise missile
- Required six support chips versus 20 for the 8008
- Introduced March 1976
- Clock rate 5 MHz
- 0.37 MIPS
- Bus Width 8 bits data, 16 bits address
- Depletion load NMOS logic
- Number of Transistors 6,500 at 3 µm
- Binary compatible downwards with the 8080.
- Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks,printers, etc...
- CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
- High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured serial I/O,3 maskable interrupts,1 Non-maskable interrupt,1 externally expandable interrupt w/[8259],status,DMA.
MCS-85 Family:
- 8085-CPU
- 8155-RAM+ 3 I/O Ports+Timer "Active Low CS"
- 8156-RAM+ 3 I/O Ports+Timer "Active High CS"
- 8185-SRAM
- 8202-Dynamic RAM Controller
- 8203-Dynamic RAM Controller
- 8205-1 Of 8 Binary Decoder
- 8206-Error Detection & Correction Unit
- 8207-DRAM Controller
- 8210-TTL To MOS Shifter & High Voltage Clock Driver
- 8212-8 Bit I/O Port
- 8216-4 Bit Parallel Bidirectional Bus Driver
- 8219-Bus Controller
- 8222-Dynamic RAM Refresh Controller
- 8226-4 Bit Parallel Bidirectional Bus Driver
- 8231-Arithmetic Processing Unit
- 8232-Floating Point Processor
- 8237-DMA Controller
- 8251-Communication Controller
- 8253-Programmable Interval Timer
- 8254-Programmable Interval Timer
- 8255-Programmable Peripheral Interface
- 8256-Multifunction Support Controller
- 8257-DMA Controller
- 8259-Programmable Interrupt Controller
- 8271-Programmable Floppy Disk Controller
- 8272-Single/Double Density Floppy Disk Controller
- 8273-Programmable HDLC/SDLC Protocol Controller
- 8274-Multi-Protocol Serial Controller
- 8275-CRT Controller
- 8276-Small System CRT Controller
- 8278-Programmable KeyBoard Interface
- 8279-KeyBoard/Display Controller
- 8282-8-bit Non-Inverting Latch with Output Buffer
- 8283-8-bit Inverting Latch with Output Buffer
- 8291-GPIB Talker/Listener
- 8292-GPIB Controller
- 8293-GPIB Transceiver
- 8294-Data Encryption/Decryption Unit+1 O/P Port
- 8295-Dot Matrix Printer Controller
- 8296-GPIB Transceiver
- 8297-GPIB Transceiver
- 8355-16,384-bit (2048 x 8) ROM with I/O
- 8604-4096-bit (512 x 8) PROM
- 8702-2K-bit (256 x 8 ) PROM
- 8755-EPROM+2 I/O Ports
Microcontrollers :
- Single accumulator Harvard architecture
MCS-48 Family
- 8020-Single-Component 8-Bit Microcontroller
- 8021-Single-Component 8-Bit Microcontroller
- 8022-Single-Component 8-Bit Microcontroller With On Chip A/D Converter
- 8031-Single-Component 8-Bit Microcontroller
- 8035-Single-Component 8-Bit Microcontroller
- 8039-Single-Component 8-Bit Microcontroller
- 8040-Single-Component 8-Bit Microcontroller
- 8041-Universal Peripheral Interface 8-Bit Slave Microcontroller
- 8641-Universal Peripheral Interface 8-Bit Slave Microcontroller
- 8741-Universal Peripheral Interface 8-Bit Slave Microcontroller
- 8042-Universal Peripheral Interface 8-Bit Slave Microcontroller
- 8242-Universal Peripheral Interface 8-Bit Slave Microcontroller
- 8742-Universal Peripheral Interface 8-Bit Slave Microcontroller
- 8243-Input/Output Expander
- 8044-High Performance 8-Bit Microcontroller With On-Chip Serial Communication controller
- 8344-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
- 8744-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
- 8048-Single-Component 8-Bit Microcontroller
- 8748-Single-Component 8-Bit Microcontroller
- 8049-Single-Component 8-Bit Microcontroller
- 8749-Single-Component 8-Bit Microcontroller
- 8050-Single-Component 8-Bit Microcontroller
- Single accumulator Harvard architecture
MCS-51 Family
- 8031-8-Bit Control-Oriented Microcontroller
- 8032-8-Bit Control-Oriented Microcontroller
- 8051-8-Bit Control-Oriented Microcontroller
- 8052-8-Bit Control-Oriented Microcontroller
- 8054-8-Bit Control-Oriented Microcontroller
- 8058-8-Bit Control-Oriented Microcontroller
- 8351-8-Bit Control-Oriented Microcontroller
- 8352-8-Bit Control-Oriented Microcontroller
- 8354-8-Bit Control-Oriented Microcontroller
- 8358-8-Bit Control-Oriented Microcontroller
- 8751-8-Bit Control-Oriented Microcontroller
- 8752-8-Bit Control-Oriented Microcontroller
- 8754-8-Bit Control-Oriented Microcontroller
- 8758-8-Bit Control-Oriented Microcontroller
- 80151-8-Bit Control-Oriented Microcontroller
- 83151-8-Bit Control-Oriented Microcontroller
- 87151-8-Bit Control-Oriented Microcontroller
- 80152-8-Bit Control-Oriented Microcontroller
- 83152-8-Bit Control-Oriented Microcontroller
- 80251-8-Bit Control-Oriented Microcontroller
- 83251-8-Bit Control-Oriented Microcontroller
- 87251-8-Bit Control-Oriented Microcontroller
MCS-96 Family
The bit-slice processor
3000 Family
Introduced 3rd Qtr, 1974 Members of the family
- 3001-Microcontrol Unit
- 3002-2-bit Arithmetic Logic Unit slice
- 3003-Look-ahead Carry Generator
- 3205-High-performance 6-bit Latch
- 3207-Quad Bipolar-to-MOS Level Shifter and Driver
- 3208-Hex Sense Amp and Latch for MOS Memories
- 3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
- 3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
- 3212-Multimode Latch Buffer
- 3214-Interrupt Control Unit
- 3216-Parallel,Inverting Bi-Directional Bus Driver
- 3222-Refresh Controller for 4K NMOS DRAMs
- 3226-Parallel,Inverting Bi-Directional Bus Driver
- 3232-Address Multiplexer and Refresh Counter for 4K DRAMs
- 3235-Quad Bipolar-to-MOS Driver
- 3242-Address Multiplexer and Refresh Counter for 16K DRAMs
- 3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
- 3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
- 3404-High-performance 6-bit Latch
- 3408-Hex Sense Amp and Latch for MOS Memories
Bus Width 2-n bits data/address (depending on number of slices used)
iPLDs:Intel Programmable Logic Devices
PLDs Family
- iFX780-10ns FLEXlogic FPGA With SRAM Option
- 85C220-80 And 66 Fast Registerd bandwidth 8-Macrocell PLDs
- 85C224-80 And 66 Fast Registerd bandwidth 8-Macrocell PLDs
- 85C22V10-Fast 10-Macrocell CHMOS μPLD
- 85C060-Fast 16-Macrocell CHMOS PLD
- 85C090-Fast 24-Macrocell CHMOS PLD
- 85C508-Fast 1-Micron CHMOS Decoder/Latch μPLD
- 85C960-Programmable Bus Control PLD
- 5AC312-1-Micron CHMOS EPLD
- 5AC324-1-Micron CHMOS EPLD
- 5C121-EPLD
- 5C031-300 Gate CMOS PLD
- 5C032-8-Macrocell PLD
- 5C060-16-Macrocell PLD
- 5C090-24-Macrocell PLD
- 5C180-48-Macrocell PLD
Signal Processor
2900 Family
- 2910-PCM CODEC – µ LAW
- 2911-PCM CODEC – A LAW
- 2912-PCM Line Filters
- 2914-Combination Codec/Filter
- 2920-Signal Processor
- 2921-ROM Signal Processor
- 2951-CHMOS Advanced Telecommunication Controller
- 2952-Integrated I/O Controller
- 2970-Single Chip Modem
Digital Clocks Processor
5000 Family
These devices are CMOS technology.
- 5101-1024-bit (256 x 4) Static RAM
- 5201/5202-LCD Decoder-Driver
- 5203 LCD Driver.
- 5204-Time Seconds/Date LCD Decoder-Driver
- 5234-Quad CMOS-to-MOS Level Shifter and Driver for 4K NMOS RAMs
- 5235-Quad CMOS TTL-to-MOS Level Shifter and Driver for 4K NMOS
- 5244-Quad CCD Clock Driver
- 5801-Low Power Oscillator-Divider
- 5810-Single Chip LCD Time/Seconds/Date Watch Circuit
- 5814 4-Digit LCD.
- 5816 6-Digit LCD.
- 5830 6-Digit LCD + Chronograph Business Sold.
The 16-bit processors: origin of x86
8086
- Introduced June 8, 1978
- Clock rates:
5 MHz with 0.33 MIPS
8 MHz with 0.66 MIPS
10 MHz with 0.75 MIPS - The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
- Bus Width 16 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Up to 10X the performance of 8080 (typically lower)
- Used in portable computing, and the IBM PS/2 Model 25 and Model 30
- Used segment registers to access more than 64 KB of data at once, bane of programmers' existence for years to come
- Introduced June 1, 1979
- Clock rates:
4.77 MHz with 0.33 MIPS
9 MHz with 0.75 MIPS - Internal architecture 16 bits
- External bus Width 8 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
- Used in IBM PCs and PC clones
MCS-86 Family
- 8086-CPU
- 8087-Math-CoProcessor
- 8088-CPU
- 8089-Input/Output Co-Processor
- 8208-Dynamic RAM Controller
- 8284-Clock Generator & Driver
- 8286-Octal Bus Transceiver
- 8287-Octal Bus Transceiver
- 8288-Bus Controller
- 8289-Bus Arbiter
- Introduced 1982
- Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
- Used in several MS-DOS non-PC-Compatible computers including RM Nimbus, Tandy 2000
- Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
- Later renamed the iAPX 186
- A version of the 80186 with an 8-bit external data bus
- Later renamed the iAPX 188
- Introduced February 1, 1982
- Clock rates:
6 MHz with 0.9 MIPS
8 MHz, 10 MHz with 1.5 MIPS
12.5 MHz with 2.66 MIPS - 16 MHz, 20 MHz and 25 MHz available.
- Bus Width 16 bits
- Included memory protection hardware to support multitasking operating systems with per-process address space
- Number of Transistors 134,000 at 1.5 µm
- Addressable memory 16 MB (16 MB)
- Added protected-mode features to 8086 with essentially the same instruction set
- 3-6X the performance of the 8086
- Widely used in IBM-PC AT and AT clones at the time
32-bit processors: the non-x86 microprocessors
iAPX 432
- Introduced January 1, 1981 as Intel's first 32-bit microprocessor
- Multi-chip CPU; Intel's first 32-bit microprocessor
- Object/capability architecture
- Microcoded operating system primitives
- One terabyte virtual address space
- Hardware support for fault tolerance
- Two-chip General Data Processor (GDP), consists of 43201 and 43202
- 43203 Interface Processor (IP) interfaces to I/O subsystem
- 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
- 43205 Memory Control Unit (MCU)
- Architecture and execution unit internal data paths 32 bit
- Clock rates:
5 MHz
7 MHz
8 MHz
- Introduced April 5, 1988
- RISC-like 32-bit architecture
- Predominantly used in embedded systems
- Evolved from the capability processor developed for the BiiN joint venture with Siemens
- Many variants identified by two-letter suffixes.
80386SX (chronological entry)
80376 (chronological entry)
- Introduced February 27, 1989
- Intel's first superscalar processor
- RISC 32/64-bit architecture, with pipeline characteristics very visible to programmer
- Used in Intel Paragon massively parallel supercomputer
- Introduced August 23, 2000
- 32-bit RISC microprocessor based on the ARM architecture
- Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.
32-bit processors: the 80386 range
80386DX
- Introduced October 17, 1985
- Clock rates:
16 MHz with 5 to 6 MIPS
20 MHz with 6 to 7 MIPS, introduced 16 February 1987
25 MHz with 8.5 MIPS, introduced 4 April 1988
33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989
Bus Width 32 bits - Number of Transistors 275,000 at 1 µm
- Addressable memory 4 GB (4 GB)
- Virtual memory 64 TB (64 TiB)
- First x86 chip to handle 32-bit data sets
- Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
- Used in Desktop computing
80960 (i960) (chronological entry)
- Introduced June 16, 1988
- Clock rates:
16 MHz with 2.5 MIPS
20 MHz with 2.5 MIPS, 25 MHz with 2.7 MIPS, introduced 25 January 1989
33 MHz with 2.9 MIPS, introduced 26 October 1992 - Internal architecture 32 bits
- External data bus width 16 bits
- External address bus width 24 bits
- Number of Transistors 275,000 at 1 µm
- Addressable memory 16 MB
- Virtual memory 32 GB
- Narrower buses enable low-cost 32-bit processing
- Used in entry-level desktop and portable computing
- No Math Co-Processor
- Introduced January 16, 1989; Discontinued June 15, 2001
- Variant of 386 intended for embedded systems
- No "real mode", starts up directly in "protected mode"
- Replaced by much more successful 80386EX from 1994
80860 (i860) (chronological entry)
- Introduced February 27, 1989
80486DX (chronological entry)
- Introduced October 15, 1990
- Clock rates:
20 MHz with 4.21 MIPS
25 MHz with 5.3 MIPS, introduced 30 September 1991 - Internal architecture 32 bits
- External bus width 16 bits
- Number of Transistors 855,000 at 1 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- First chip specifically made for portable computers because of low power consumption of chip
- Highly integrated, includes cache, bus, and memory controllers
80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)
- Introduced 1991–1994
- Introduced August 1994
- Variant of 80386SX intended for embedded systems
- Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
- On-chip peripherals:
Clock and power mgmt
Timers/counters
Watchdog timer
Serial I/O units (sync and async) and parallel I/O
DMA
RAM refresh
JTAG test logic - Significantly more successful than the 80376
- Used aboard several orbiting satellites and microsatellites
- Used in NASA's FlightLinux project
32-bit processors: the 80486 range
80486DX
- Introduced April 10, 1989
- Clock rates:
25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced 7 May 1990
50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced 24 June 1991 - Bus Width 32 bits
- Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- Level 1 cache of 8 KB on chip
- Math coprocessor on chip
- 50X performance of the 8088
- Used in Desktop computing and servers
- Family 4 model 3
80386SL (chronological entry)
- Introduced October 15, 1990
- Introduced April 22, 1991
- Clock rates:
16 MHz with 13 MIPS
20 MHz with 16.5 MIPS, introduced 16 September 1991
25 MHz with 20 MIPS (12 SPECint92), introduced 16 September 1991
33 MHz with 27 MIPS (15.86 SPECint92), introduced 21 September 1992 - Bus Width 32 bits
- Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathco in the chip and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 turned on)
- Used in low-cost entry to 486 CPU desktop computing
- Upgradable with the Intel OverDrive processor
- Family 4 model 2
- Introduced March 3, 1992
- Clock rates:
40 MHz
50 MHz
66 MHz
100 MHz (This was only made a short time due to high failure rates.)
- Introduced November 9, 1992
- Clock rates:
20 MHz with 15.4MIPS
25 MHz with 19 MIPS
33 MHz with 25 MIPS - Bus Width 32 bits
- Number of Transistors 1.4 million at 0.8 µm
- Addressable memory 4 GB
- Virtual memory 1 TB
- Used in notebook computers
- Family 4 model 3
Pentium (chronological entry)
- Introduced March 7, 1994
- Clock rates:
75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2) - Number of Transistors 1.6 million at 0.6 µm
- Bus width 32 bits
- Addressable memory 4 GB
- Virtual memory 64 TB
- Pin count 168 PGA Package, 208 sq ftP Package
- Die size 345 mm²
- Used in high performance entry-level desktops and value notebooks
- Family 4 model 8
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